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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13704-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90590/590G Series
MB90591/591G/F591A/F591G/594/594G/F594A/F594G MB90V590A/V590G
s DESCRIPTION
The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller, and sound generator. *1 : Controller Area Network (CAN) - License of Robert Bosch GmbH *2 : F2MC stands for FUJITSU Flexible Microcontroller.
s PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90590/590G Series
s FEATURES
* Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) * Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed : 4-byte instruction queue * Enhanced interrupt function : 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) : Up to 10 channels * Embedded ROM size and types Mask ROM : 256 Kbytes/384 Kbytes Flash ROM : 256 Kbytes/384 Kbytes Embedded RAM size : 6 Kbytes/8 Kbytes * Flash ROM Supports automatic programming, Embedded Algorithm TM* Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Clock mode Hardware stand-by mode * Process 0.5m CMOS technology * I/O port General-purpose I/O ports : 78 ports * Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit x 6 channels 16-bit re-load timer : 2 channels
2
MB90590/590G Series
* 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 6 channels Output compare : 6 channels * Extended I/O serial interface : 1 channel * UART (3 channels) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. * Stepping motor controller (4 channels) * External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. * FULL-CAN interfaces : 2 Conforming to Version 2.0 Part A and Part B Flexible message buffering (mailbox and FIFO buffering can be mixed) * Sound generator * 18-bit Time-base counter * Clock timer : 1 channel * External bus interface : Maximum address space 16 Mbytes * : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
3
MB90590/590G Series
s PRODUCT LINEUP
Features Classification ROM size RAM size Emulator-specific power supply *1 MB90591/591G/594/594G Mask ROM product 384/256 Kbytes 8/6 Kbytes MB90F591A/F591G/ F594A/F594G Flash ROM product 384/256 Kbytes Boot block Hard-wired reset vector 8/6 Kbytes MB90V590A/V590G Evaluation product None 8 Kbytes None
CPU functions
The number of instructions : 340 Instruction bit length : 8 bits, 16 bits Instruction length : 1 byte to 7 bytes Data bit length : 1 bit, 8 bits, 16 bits Minimum execution time : 62.5 ns (at machine clock frequency of 16 MHz) Interrupt processing time : 1.5 s (at machine clock frequency of 16 MHz, minimum value) Clock synchronized transmission (500 Kbps / 1 Mbps / 2 Mbps) Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500 /500000 bps at machine clock frequency of 16 MHz) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. Conversion precision : 8/10-bit can be selectively used. Number of inputs : 8 One-shot conversion mode (converts selected channel once only) Scan conversion mode (converts two or more successive channels and can program up to 8 channels) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels : 6 (8/16-bit x 6 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval : fsys, fsys/21, fsys/22, fsys/23, fsys/24, 128s (at oscillation of 4 MHz, fsys = system clock frequency of 16 MHz, fosc = oscillation clock frequency) Number of channels : 2 Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function
UART (3 channels)
8/10-bit A/D converter
8/16-bit PPG timers (6 channels)
16-bit Reload timer
16-bit I/O timer
16-bit Number of channels : 6 (8/16-bit x 6 channels) Output compares Pin input factor : A match signal of compare register Input captures Number of channels : 6 Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
4
MB90590/590G Series
(Continued)
Features MB90591/591G/594/594G MB90F591A/F591G/ F594A/F594G MB90V590A/V590G
CAN Interface
Number of channels : 2 Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps CAN bit timing setting : MB90xxx : TSEG2 RSJW+2TQ MB90xxxG : TSEG2 RSJW
Stepping motor controller Four high current outputs for each channel (4 channels) Synchronized two 8-bit PWM's for each channel External interrupt circuit Number of inputs : 8 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. 8-bit PWM signal is mixed with tone frequency from 8-bit reload counter PWM frequency : 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz) Tone frequency : PWM frequency / 2 / (reload value + 1) Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock frequency of 16 MHz) LSB first/MSB first Directly operates with the system clock Read/Write accessible Second/Minute/Hour registers Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Supports automatic programming, Embedded Algorithm TM and Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Writer from Minato Electronics Inc. Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by CMOS 5 V10 % (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G) 5 V5 % (MB90F591G, MB90591G, MB90F591A, MB90591) QFP-100 PGA-256
Sound generator
Extended I/O serial interface Clock timer Watchdog timer
Flash Memory
Low-power consumption (stand-by) mode Process Power supply voltage for operation*2 Package
*1 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *2 : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") 5
MB90590/590G Series
s PIN ASSIGNMENT
(Top view)
P13/OUT5 P12/OUT4 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P16/SGO P17/SGA P15/TX1 P14/RX1 P04/IN4 P03/IN3 P02/IN2 P01/IN1 P05/IN5 P00/IN0
Vcc
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
X0
P20 P21 P22 P23 P24/INT4 P25/INT5 P26/INT6 P27/INT7 P30 P31 Vss P32 P33 P34/SOT0
P35/SCK0 P36/SIN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Vss
X1
P95/INT3 P94/INT2 P93/INT1 RST P92/INT0 P91/RX0 P90/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS HST MD2
P37/SIN1 P40/SCK1 P41/SOT1 P42/SOT2 P43/SCK2 P44/SIN2 Vcc P45/SCIN3 P46/SCK3 P47/SOT3 C P50/PPG0 P51/PPG1 P52/PPG2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 P57/TOT/WOT
49 MD0
P55/PPG5/ADTG
P54/PPG4
AVRH
P60/AN0
P61/AN1
P62/AN2
P63/AN3
Vss
P64/AN4
P65/AN5
AVRL
AVcc
AVss
P66/AN6
P67/AN7
P56/TIN
P53/PPG3
(FPT-100P-M06)
6
MD1
50
MB90590/590G Series
s PIN DESCRIPTION
No. 82 83 77 52 85 to 90 Pin name X0 X1 RST HST P00 to P05 IN0 to IN5 P06 to P07, P10 to P13 91 to 96 OUT0 to OUT5 P14 RX1 P15 98 TX1 P16 99 SGO P17 100 SGA P20 to P23 P24 to P27 INT4 to INT7 P30 to P31 P32 to P33 P34 14 SOT0 P35 15 SCK0 D D D D D D Circuit type A B C D Oscillator pin Reset input Hardware standby input General purpose I/O Inputs for the Input Captures General purpose I/O Outputs for the Output Compares. To enable the signal outputs, the corresponding bits of the Port Direction registers should be set to "1". General purpose I/O RX input for CAN Interface 1 General purpose I/O TX output for CAN Interface 1. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose I/O SGO output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose I/O SGA output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose I/O General purpose I/O External interrupt input for INT4 to INT7 General purpose I/O General purpose I/O General purpose I/O SOT output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose I/O SCK input/output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". Function
97
D
1 to 4 5 to 8 9 to 10 12 to 13
D D D D
(Continued)
7
MB90590/590G Series
No. 16 17 18 19 20 21 22 24 25 26
Pin name P36 SIN0 P37 SIN1 P40 SCK1 P41 SOT1 P42 SOT2 P43 SCK2 P44 SIN2 P45 SIN3 P46 SCK3 P47 SOT3 P50 to P55 PPG0 to PPG5, ADTG P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P56 TIN P57
Circuit type D D D D D D D D D D General purpose I/O SIN input for UART 0 General purpose I/O SIN input for UART 1 General purpose I/O SCK input/output for UART 1 General purpose I/O SOT output for UART 1 General purpose I/O SOT output for UART 2 General purpose I/O SCK input/output for UART 2 General purpose I/O SIN input for UART 2 General purpose I/O SIN input for the Serial I/O General purpose I/O
Function
SCK input/output for the Serial I/O General purpose I/O SOT output for the Serial I/O General purpose I/O Outputs for the Programmable Pulse Generators. Pin number 33 is also shared with ADTG input for the external trigger of the A/D Converter. General purpose I/O Inputs for the A/D Converter General purpose I/O Inputs for the A/D Converter General purpose I/O TIN input for the 16-bit Reload Timers General purpose I/O TOT output for the 16-bit Reload Timers and WOT output for the Watch Timer. Only one of three output enable flags in these peripheral blocks can be set at a time. Otherwise the output signal has no meaning.
28 to 33
D
38 to 41 43 to 46 47
E E D
48
TOT/WOT
D
(Continued)
8
MB90590/590G Series
No. Pin name P70 to P73 54 to 57 PWM1P0, PWM1M0, PWM2P0, PWM2M0 P74 to P77 59 to 62 PWM1P1, PWM1M1, PWM2P1, PWM2M1 P80 to P83 64 to 67 PWM1P2, PWM1M2, PWM2P2, PWM2M2 P84 to P87 69 to 72 PWM1P3, PWM1M3, PWM2P3, PWM2M3 P90 TX0 P91 RX0 P92 INT0 P93 INT1 P94 INT2 P95 INT3 DVCC DVSS F F F F Circuit type General purpose I/O Function
Output for Stepping Motor Controller channel 0.
General purpose I/O
Output for Stepping Motor Controller channel 1.
General purpose I/O
Output for Stepping Motor Controller channel 2.
General purpose I/O
Output for Stepping Motor Controller channel 3.
74 75 76 78 79 80 58, 68 53, 63, 73
D D D D D D Power supply Power supply
General purpose I/O TX output for CAN Interface 0 General purpose I/O RX input for CAN Interface 0 General purpose I/O External interrupt input for INT0 General purpose I/O External interrupt input for INT1 General purpose I/O External interrupt input for INT2 General purpose I/O External interrupt input for INT3 Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) Dedicated ground pins for the high current output buffers (Pin No. 54 to 72) Power supply for analog circuit pin When turning this power supply on or off, always be sure to first apply electric potential equal to or greater than AVCC to VCC. Ground level for analog circuit
34
AVCC
37
AVSS
(Continued)
9
MB90590/590G Series
(Continued) No.
35
Pin name AVRH
Circuit type Power supply Power supply C G Power supply Power supply
Function Reference voltage input pin for analog circuit When turning this power supply on or off, always be sure to first apply electric potential equal to or greater than AVRH to AVCC. Reference voltage input pin for analog circuit Operating mode selection input pins Connect directly to VCC or VSS. Operating mode selection input pin Connect directly to VCC or VSS. This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. Power supply (5.0 V) input pin for digital circuit Power supply (GND) input pin for digital circuit
36 49, 50 51 27 23, 84 11,42,81
AVRL MD0, MD1 MD2 C VCC VSS
10
MB90590/590G Series
s I/O CIRCUIT TYPE
Circuit Type
X1 Clock Input
Circuit
Remarks * Oscillation feedback resistor : 1 M approx.
X0
A
HARD,SOFT STANDBY CONTROL
* Hysteresis input with pull-up resistor : 50 k approx. B R (pull-up) R HYS
* Hysteresis input C R HYS
VCC P-ch N-ch
* CMOS output * Hysteresis input
D
R
HYS
(Continued)
11
MB90590/590G Series
(Continued) Circuit Type
Circuit Vcc P-ch N-ch
Remarks * CMOS output * Hysteresis input * Analog input
E P-ch Analog input N-ch R HYS
* CMOS high current output * Hysteresis input P-ch High current F N-ch
R
HYS
R G R (pull-down)
HYS
* Hysteresis input with pull-down resistor : 50 k approx. * Flash version does not have pull-down resistor.
12
MB90590/590G Series
s HANDLING DEVICES
(1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than Vcc or lower than Vss is applied to an input or output pin. * A voltage higher than the rated voltage is applied between Vcc and Vss. * The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. (2) Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) Using external clock To use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock. MB90590/590G Series X0 X1
Using external clock
13
MB90590/590G Series
(4)Power supply pins (Vcc/Vss) In products with multiple VCC or VSS pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. Vcc Vss
Vcc Vss Vcc
Vss
MB90590/590G Vcc Series
Vss
Vss
Vcc
(5) Pull-up/down resistors The MB90590/590G Series does not support internal pull-up/down resistors. Use external components where needed. (6) Crystal Oscillator Circuit Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuits do not cross the lines of other circuits. A printed circuit board artwork surrounding the X0 and X1 pins with a ground area for stabilizing the operation is highly recommended. (7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). (8) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
14
MB90590/590G Series
(9) N.C. Pin The N.C. (internally connected) pin must be opened for use. (10) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V). (11) Indeterminate outputs from ports 0 and 1 (without MB90F591G/591G, MB90F594G) During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. * If RST pin is "H", the outputs become indeterminate. * If RST pin is "L", the outputs become high-impedance. Pay attention to the port output timing shown as follow. RST pin is "H" Oscillation setting time*2 Power-on reset*1 Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal
Period of indeterminated
*1 : Power-on reset time : Period of "clock frequency x 217" (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : Period of "clock frequency x 218" (Clock frequency of 16 MHz : 16.38ms) RST pin is "L" Oscillation setting time2 Power-on reset1 Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1 : Power-on reset time : Period of "clock frequency x 217" (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : Period of "clock frequency x 218" (Clock frequency of 16 MHz : 16.38ms) 15
MB90590/590G Series
(12) Initialization The device contains internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (13) Directions of "DIV A, Ri" and "DIVW A, RWi" instructions In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi"), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00 H". If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than "00 H", the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (15) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
16
MB90590/590G Series
s BLOCK DIAGRAM
X0,X1 RST HST
Clock Controller
F2MC-16LX CPU
RAM 6/8 K
16-bit I/O Timer 16-bit Input Capture 6ch IN0 to IN5
ROM/Flash
256 K/384 K
16-bit Output Compare 4ch
OUT0 to OUT5
Prescaler x 3
SOT0 to SOT2 SCK0 to SCK2 SIN0 to SIN2 UART 3ch
8/16-bit PPG 6ch
PPG0 to PPG5
Prescaler
CAN 2ch
RX0, RX1 TX0, TX1
SOT3 SCK3 SIN3 AVCC AVSS AN0 to AN7 AVRH AVRL ADTG
Serial I/O PWM1M0 to PWM1M3 SMC 4ch PWM1P0 to PWM1P3 PWM2M0 to PWM2M3 PWM2P0 to PWM2P3 DVCC DVSS
10-bit ADC 8ch
F2MC-16 Bus
TIN TOT/WOT
16-bit Reload Timer 2ch
External Interrupt Circuit 8ch
INT0 to INT7
Sound Generator
SGO SGA
Watch Timer
17
MB90590/590G Series
s MEMORY SPACE
The memory space of the MB90590/590G Series is shown below
MB90V590A/V590G FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H MB90594/F594A/ 594G/F594G ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H MB90591/F591A/ 591G/F591G ROM (FF bank) ROM (FE bank) ROM (FD bank)
ROM (FB bank) ROM (FA bank) ROM (F9 bank)
00FFFFH 004000H
ROM (Image of FF bank)
00FFFFH 004000H
ROM (Image of FF bank)
00FFFFH 004000H
ROM (Image of FF bank)
0028FFH 002100H 0020FFH 001FFFH 001900H 0018FFH
RAM 2K
0028FFH 002100H 0020FFH 001FFFH 001900H 0018FFH Peripheral 001FFFH 001900H 0018FFH
RAM 2K
Peripheral
Peripheral
RAM 6K 000100H 0000BFH 000000H Peripheral 000100H 0000BFH 000000H
RAM 6K 000100H Peripheral 0000BFH 000000H
RAM 6K
Peripheral
Memory space map Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.
18
MB90590/590G Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH to 1FH 20H 21H 22H 23H 24H 25H 26H 27H Serial Mode Control Register 0 Serial Status Register 0
Serial Input/Output Data Register 0
Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 7 Data Register Port 8 Data Register Port 9 Data Register Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Port 3 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Port 7 Direction Register Port 8 Direction Register Port 9 Direction Register Analog Input Enable Register
Abbreviation Access PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 ADER UMC0 USR0 UIDR0/ UODR0 URD0 UMC1 USR1 UIDR1/ UODR1 URD1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 6, A/D
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _ _ XXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B
Reserved
Reserved Reserved
UART0
XXXXXXXXB 0 0 0 0 0 0 0XB 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B
Rate and Data Register 0 Serial Mode Control Register 1 Serial Status Register 1
Serial Input/Output Data Register 1
UART1
XXXXXXXXB 0 0 0 0 0 0 0XB
Rate and Data Register 1
(Continued)
19
MB90590/590G Series
Address 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H
Register Serial Mode Control Register 2 Serial Status Register 2 Serial Input/Output Data Register 2 Rate and Data Register 2 Serial Mode Control Register (low-order) Serial Mode Control Register (high-order) Serial Data Register Edge Selector Register External Interrupt Enable Register
External Interrupt Request Register
Abbreviation Access UMC2 USR2 UIDR2/ UODR2 URD2 SMCS SMCS SDR SES ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 PPGC2 PPGC3 PPG23 PPGC4 PPGC5 PPG45 PPGC6 PPGC7 PPG67 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral
Initial value 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B
UART2
XXXXXXXXB 0 0 0 0 0 0 0XB _ _ _ _0 0 0 0B
Serial I/O
0 0 0 0 0 0 1 0B XXXXXXXXB _ _ _ _ _ _ _0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 0 XXB
External Interrupt Level Register External Interrupt Level Register A/D Control Status Register 0 A/D Control Status Register 1 A/D Data Register 0 A/D Data Register 1
PPG0 Operation Mode Control Register PPG1 Operation Mode Control Register
External Interrupt
A/D Converter
PPG0,1 Output Pin Control Register
16-bit Programmable 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B Pulse Generator 0/1 0 0 0 0 0 0 0 0B 0 _ 0 0 0 _ _1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 2/3 0 0 0 0 0 0 0 0B 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 4/5 0 0 0 0 0 0 0 0B 16-bit Programmable 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B Pulse Generator 6/7 0 0 0 0 0 0 0 0B
Reserved
PPG2 Operation Mode Control Register PPG3 Operation Mode Control Register
PPG2,3 Output Pin Control Register
Reserved
PPG4 Operation Mode Control Register PPG5 Operation Mode Control Register
PPG4,5 Output Pin Control Register
Reserved
PPG6 Operation Mode Control Register PPG7 Operation Mode Control Register
PPG6,7 Output Pin Control Register
Reserved
(Continued)
20
MB90590/590G Series
Address 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH
Register
PPG8 Operation Mode Control Register PPG9 Operation Mode Control Register
Abbreviation Access PPGC8 PPGC9 PPG89 PPGCA PPGCB PPGAB R/W R/W R/W R/W R/W R/W
Peripheral
Initial value
PPG8,9 Output Pin Control Register
0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 8/9 0 0 0 0 0 0 0 0B 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator A/B 0 0 0 0 0 0 0 0B
Reserved
PPGA Operation Mode Control Register PPGB Operation Mode Control Register
PPGA,B Output Pin Control Register
Reserved Timer Control Status Register 0 (low-order)
Timer Control Status Register 0 (high-order)
TMCSR0 TMCSR0 TMCSR1 TMCSR1 ICS01 ICS23 ICS45
R/W 16-bit Reload Timer 0 R/W R/W 16-bit Reload Timer 1 R/W R/W R/W R/W Input Capture 0/1 Input Capture 2/3 Input Capture 4/5
0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
Timer Control Status Register 1 (low-order)
Timer Control Status Register 1 (high-order)
Input Capture Control Status Register 0/1 Input Capture Control Status Register 2/3 Input Capture Control Status Register 4/5 Output Compare Control Status Register 0 Output Compare Control Status Register 1 Output Compare Control Status Register 2 Output Compare Control Status Register 3 Output Compare Control Status Register 4 Output Compare Control Status Register 5
Sound Control Register (low-order) Sound Control Register (high-order)
Reserved OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 SGCR SGCR R/W Output Compare 0/1 R/W R/W Output Compare 2/3 R/W R/W Output Compare 4/5 R/W R/W R/W Sound Generator _ _ _ 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 _ _ _ _ _ _ 0B _ _ _ 0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _0 0 0 0 0B 0 0 0 0 _ _ 0 0B 0 0 0 0 _ _ 0 0B
(Continued)
21
MB90590/590G Series
Address 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H to 6CH 6DH 6EH 6FH 70H to 8FH 90H to 9DH 9EH 9FH A0H A1H A2H to A7H A8H A9H AAH to ADH Flash Memory Control Status Register (Flash product only. Otherwise reserved)
Watchdog Timer Control Register Time Base Timer Control Register
Register Watch Timer Control Register (low-order) Watch Timer Control Register (high-order) PWM Control Register 0
Abbreviation Access WTCR WTCR PWC0 R/W
Peripheral
Initial value 0 0 0 _ _ 0 0 0B
Watch Timer R/W R/W Reserved Stepping Motor Controller 0 Stepping Motor Controller 1 Stepping Motor Controller 2 Stepping Motor Controller 3 Prescaler (Serial I/O) I/O Timer ROM Mirror 0 0 0 0 0 0 0 0B 0 0 0 0 0 _ _ 0B
PWM Control Register 1
PWC1
R/W Reserved
0 0 0 0 0 _ _ 0B
PWM Control Register 2
PWC2
R/W Reserved
0 0 0 0 0 _ _ 0B
PWM Control Register 3
PWC3
R/W Reserved
0 0 0 0 0 _ _ 0B
Serial I/O Prescaler Register Timer Control Status Register ROM Mirror Function Select Register
CDCR TCCS ROMM
R/W R/W W
0 XXX 1 1 1 1B 0 0 0 0 0 0 0 0B XXXXXXX1B
Reserved for CAN Interface 0/1. Refer to section about CAN Controller Reserved Program Address Detection Control Status Register
Delayed Interrupt/Release Register
PACSR DIRR LPMCR CKSCR WDTC TBTC
R/W R/W R/W R/W Reserved R/W R/W Reserved
Address Match Detection Function Delayed Interrupt Low Power Controller Low Power Controller Watchdog Timer Time Base Timer
0 0 0 0 0 0 0 0B _ _ _ _ _ _ _ 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B XXXXX 1 1 1B 1 - - 0 0 1 0 0B
Low Power Mode Control Register
Clock Selection Register
AEH
FMCS
R/W
Flash Memory
0 0 0 X 0 0 0 0B
AFH
Reserved
(Continued)
22
MB90590/590G Series
Address B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH 1900H 1901H 1902H 1903H 1904H 1905H 1906H 1907H 1908H 1909H 190AH 190BH 190CH 190DH 190EH 190FH
Register Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15
Abbreviation ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral
Initial value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Interrupt controller
Reserved Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit Programmable Pulse Generator 6/7 16-bit Programmable Pulse Generator 4/5 16-bit Programmable Pulse Generator 2/3 16-bit Programmable Pulse Generator 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
23
MB90590/590G Series
Address 1910H 1911H 1912H 1913H 1914H 1915H 1916H 1917H 1918H to 191FH 1920H 1921H 1922H 1923H 1924H 1925H 1926H 1927H 1928H 1929H 192AH 192BH 192CH to 192FH
Register Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register Reload L Register Reload H Register Input Capture Register 0 (low-order) Input Capture Register 0 (high-order) Input Capture Register 1 (low-order) Input Capture Register 1 (high-order) Input Capture Register 2 (low-order) Input Capture Register 2 (high-order) Input Capture Register 3 (low-order) Input Capture Register 3 (high-order) Input Capture Register 4 (low-order) Input Capture Register 4 (high-order) Input Capture Register 5 (low-order) Input Capture Register 5 (high-order)
Abbreviation Access PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB R/W R/W R/W R/W R/W R/W R/W R/W Reserved IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 IPCP4 IPCP4 IPCP5 IPCP5 R R
Peripheral 16-bit Programmable Pulse Generator 8/9
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programmable Pulse Generator A/B
XXXXXXXXB XXXXXXXXB XXXXXXXXB
XXXXXXXXB XXXXXXXXB Input Capture 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Capture 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Capture 4/5 XXXXXXXXB XXXXXXXXB
R R R R R R R R R R Reserved
(Continued)
24
MB90590/590G Series
Address 1930H 1931H 1932H 1933H 1934H 1935H 1936H 1937H 1938H 1939H 193AH 193BH 193CH to 193FH 1940H 1941H 1942H 1943H 1944H 1945H 1946H 1947H 1948H 1949H Timer 0/Reload Register 0 (low-order) Timer 0/Reload Register 0 (high-order) Timer 1/Reload Register 1 (low-order) Timer 1/Reload Register 1 (high-order) Timer Data Register (low-order) Timer Data Register (high-order) Frequency Data Register Amplitude Data Register Decrement Grade Register Tone Count Register Register Output Compare Register 0 (low-order) Output Compare Register 0 (high-order) Output Compare Register 1 (low-order) Output Compare Register 1 (high-order) Output Compare Register 2 (low-order) Output Compare Register 2 (high-order) Output Compare Register 3 (low-order) Output Compare Register 3 (high-order) Output Compare Register 4 (low-order) Output Compare Register 4 (high-order) Output Compare Register 5 (low-order) Output Compare Register 5 (high-order) Abbreviation OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 OCCP4 OCCP4 OCCP5 OCCP5 Reserved TMR0/ TMRLR0 TMR0/ TMRLR0 TMR1/ TMRLR1 TMR1/ TMRLR1 TCDT TCDT SGFR SGAR SGDR SGTR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sound Generator 16-bit Reload Timer 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Peripheral Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
16-bit Reload Timer 1
I/O Timer
(Continued)
25
MB90590/590G Series
Address 194AH 194BH 194CH 194DH 194EH 194FH 1950H 1951H 1952H 1953H 1954H 1955H 1956H 1957H 1958H 1959H 195AH 195BH 195CH 195DH 195EH 195FH 1960H to 19FFH 1A00H to 1AFFH 1B00H to 1BFFH 1C00H to 1CFFH 1D00H to 1DFFH 1E00H to 1EFFH Register Sub-second Data Register (low-order) Sub-second Data Register (middle-order) Sub-second Data Register (high-order) Second Data Register Minute Data Register Hour Data Register PWM1 Compare Register 0 PWM2 Compare Register 0 PWM1 Select Register 0 PWM2 Select Register 0 PWM1 Compare Register 1 PWM2 Compare Register 1 PWM1 Select Register 1 PWM2 Select Register 1 PWM1 Compare Register 2 PWM2 Compare Register 2 PWM1 Select Register 2 PWM2 Select Register 2 PWM1 Compare Register 3 PWM2 Compare Register 3 PWM1 Select Register 3 PWM2 Select Register 3 Abbreviation WTBR WTBR WTBR WTSR WTMR WTHR PWC10 PWC20 PWS10 PWS20 PWC11 PWC21 PWS11 PWS21 PWC12 PWC22 PWS12 PWS22 PWC13 PWC23 PWS13 PWS23 Reserved Reserved for CAN Interface 0. Refer to section about CAN Controller Reserved for CAN Interface 1. Refer to section about CAN Controller Reserved for CAN Interface 0. Refer to section about CAN Controller Reserved for CAN Interface 1. Refer to section about CAN Controller Reserved Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Stepping Motor Controller 3 Stepping Motor Controller 2 Stepping Motor Controller 1 Stepping Motor Controller 0 Watch Timer Peripheral Initial value XXXXXXXXB XXXXXXXXB _ _ _ XXXXXB __000000B __000000B ___00000B XXXXXXXXB XXXXXXXXB __000000B _0000000B XXXXXXXXB XXXXXXXXB __000000B _0000000B XXXXXXXXB XXXXXXXXB __000000B _0000000B XXXXXXXXB XXXXXXXXB __000000B _0 0 0 0 0 0 0 B
Watch Timer
(Continued)
26
MB90590/590G Series
(Continued)
Address 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 1FF6H to 1FFFH Register Program Address Detection Register 0 (low-order) Program Address Detection Register 0 (middle-order) Program Address Detection Register 0 (high-order) Program Address Detection Register 1 (low-order) Program Address Detection Register 1 (middle-order) Program Address Detection Register 1 (high-order) Abbreviation PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 Reserved Access R/W R/W R/W R/W R/W R/W Address Match Detection Function Peripheral Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B
Note : Initial value of "_" represents unused bit; "X" represents unknown value. Addresses in the rage 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results in reading "X", and any write access should not be performed.
27
MB90590/590G Series
s CAN CONTROLLERS
The CAN controller has the following features : Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmission of data frames by receiving remote frames * 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz) List of Control Registers Address CAN0 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B
28
MB90590/590G Series
List of Control Registers Address CAN0 001C00H 001C01H 001C02H 001C03H 001C04H 001C05H 001C06H 001C07H 001C08H 001C09H CAN1 001D00H 001D01H 001D02H 001D03H 001D04H 001D05H 001D06H 001D07H 001D08H 001D09H Register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation Access CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER R/W, R R/W R R/W R/W R/W R/W R/W Initial Value 00---000 0----0-1B -------- 000-0000B 00000000 00000000B -1111111 11111111B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXXB
001C0AH 001D0AH 001C0BH 001D0BH 001C0CH 001D0CH 001C0DH 001D0DH 001C0EH 001D0EH 001C0FH 001C10H 001C11H 001C12H 001C13H 001C14H 001C15H 001C16H 001C17H 001C18H 001C19H 001D0FH 001D10H 001D11H 001D12H 001D13H 001D14H 001D15H 001D16H 001D17H 001D18H 001D19H
001C1AH 001D1AH 001C1BH 001D1BH
29
MB90590/590G Series
List of Message Buffers (ID Registers) Address CAN0 001A20H 001A21H 001A22H 001A23H 001A24H 001A25H 001A26H 001A27H 001A28H 001A29H 001A2AH 001A2BH 001A2CH 001A2DH 001A2EH 001A2FH 001A30H 001A31H 001A32H 001A33H 001A34H 001A35H 001A36H 001A37H 001A38H 001A39H 001A3AH 001A3BH 001A3CH 001A3DH 001A3EH 001A3FH CAN1 001B20H 001B21H 001B22H 001B23H 001B24H 001B25H 001B26H 001B27H 001B28H 001B29H 001B2AH 001B2BH 001B2CH 001B2DH 001B2EH 001B2FH 001B30H 001B31H 001B32H 001B33H 001B34H 001B35H 001B36H 001B37H 001B38H 001B39H 001B3AH 001B3BH 001B3CH 001B3DH 001B3EH 001B3FH ID register 7 IDR7 R/W XXXXX--- XXXXXXXXB ID register 6 IDR6 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 5 IDR5 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXXB
(Continued)
30
MB90590/590G Series
(Continued) Address
CAN0 001A40H 001A41H 001A42H 001A43FH 001A44H 001A45H 001A46H 001A47H 001A48H 001A49H 001A4AH 001A4BH 001A4CH 001A4DH 001A4EH 001A4FH 001A50H 001A51H 001A52H 001A53H 001A54H 001A55H 001A56H 001A57H 001A58H 001A59H 001A5AH 001A5BH 001A5CH 001A5DH 001A5EH 001A5FH CAN1 001B40H 001B41H 001B42H 001B43H 001B44H 001B45H 001B46H 001B47H 001B48H 001B49H 001B4AH 001B4BH 001B4CH 001B4DH 001B4EH 001B4FH 001B50H 001B51H 001B52H 001B53H 001B54H 001B55H 001B56H 001B57H 001B58H 001B59H 001B5AH 001B5BH 001B5CH 001B5DH 001B5EH 001B5FH ID register 15 IDR15 R/W XXXXX--- XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 8 IDR8 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
Register
Abbreviation
Access
Initial Value XXXXXXXX XXXXXXXXB
31
MB90590/590G Series
List of Message Buffers (DLC Registers and Data Registers) Address CAN0 001A60H 001A61H 001A62H 001A63H 001A64H 001A65H 001A66H 001A67H 001A68H 001A69H 001A6AH 001A6BH 001A6CH 001A6DH 001A6EH 001A6FH 001A70H 001A71H 001A72H 001A73H 001A74H 001A75H 001A76H 001A77H 001A78H 001A79H 001A7AH 001A7BH 001A7CH 001A7DH 001A7EH 001A7FH 001A80H to 001A87H CAN1 001B60H 001B61H 001B62H 001B63H 001B64H 001B65H 001B66H 001B67H 001B68H 001B69H 001B6AH 001B6BH 001B6CH 001B6DH 001B6EH 001B6FH 001B70H 001B71H 001B72H 001B73H 001B74H 001B75H 001B76H 001B77H 001B78H 001B79H 001B7AH 001B7BH 001B7CH 001B7DH 001B7EH 001B7FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXX ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB XXXXXXXXB to XXXXXXXXB
001B80H to Data register 0 (8 bytes) 001B87H
DTR0
R/W
(Continued)
32
MB90590/590G Series
(Continued) Address
CAN0 001A88H to 001A8FH 001A90H to 001A97H 001A98H to 001A9FH 001AA0H to 001AA7H 001AA8H to 001AAFH 001AB0H to 001AB7H 001AB8H to 001ABFH 001AC0H to 001AC7H 001AC8H to 001ACFH 001AD0H to 001AD7H 001AD8H to 001ADFH 001AE0H to 001AE7H 001AE8H to 001AEFH 001AF0H to 001AF7H 001AF8H to 001AFFH CAN1
Register
Abbreviation
Access
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB 33
001B88H to Data register 1 (8 bytes) 001B8FH 001B90H to Data register 2 (8 bytes) 001B97H 001B98H to Data register 3 (8 bytes) 001B9FH 001BA0H to Data register 4 (8 bytes) 001BA7H 001BA8H to Data register 5 (8 bytes) 001BAFH 001BB0H to Data register 6 (8 bytes) 001BB7H 001BB8H to Data register 7 (8 bytes) 001BBFH 001BC0H to Data register 8 (8 bytes) 001BC7H 001BC8H to Data register 9 (8 bytes) 001BCFH 001BD0H to Data register 10 (8 bytes) 001BD7H 001BD8H to Data register 11 (8 bytes) 001BDFH 001BE0H to Data register 12 (8 bytes) 001BE7H 001BE8H to Data register 13 (8 bytes) 001BEFH 001BF0H to Data register 14 (8 bytes) 001BF7H 001BF8H to Data register 15 (8 bytes) 001BFFH
DTR1
R/W
DTR2
R/W
DTR3
R/W
DTR4
R/W
DTR5
R/W
DTR6
R/W
DTR7
R/W
DTR8
R/W
DTR9
R/W
DTR10
R/W
DTR11
R/W
DTR12
R/W
DTR13
R/W
DTR14
R/W
DTR15
R/W
MB90590/590G Series
s INTERRUPT MAP
Interrupt cause Reset INT9 instruction Exception Time Base Timer External Interrupt (INT0 to INT7) CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS 8/16 bit PPG 0/1 8/16 bit PPG 2/3 8/16 bit PPG 4/5 8/16 bit PPG 6/7 8/16 bit PPG 8/9 8/16 bit PPG A/B 16-bit Reload Timer 0 16-bit Reload Timer 1 Input Capture 0/1 Output compare 0/1 Input Capture 2/3 Output Compare 2/3 Input Capture 4/5 Output Compare 4/5 8/10 bit A/D Converter I/O Timer/Watch Timer Serial I/O Sound Generator UART 0 RX UART 0 TX UART 1 RX UART 1 TX UART 2 RX UART 2 TX Flash Memory Delayed interrupt 34 I2OS clear N/A N/A N/A N/A *1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A *1 *1 *1 *1 *1 *1 *1 *1 *1 N/A *1 N/A *2 *1 *2 *1 *2 *1 N/A N/A Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
MB90590/590G Series
*1 : The interrupt request flag is cleared by the I2OS interrupt clear signal. *2 : The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available. N/A : The interrupt request flag is not cleared by the I2OS interrupt clear signal. Notes : * For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are cleared by the I2OS interrupt clear signal. * At the end of I2OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the I2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the I2OS clear signal caused by the first event. So it is recommended not to use the I2OS for this interrupt number. * If I2OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same I2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the I2OS, the other interrupt should be disabled.
35
MB90590/590G Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter Symbol VCC AVCC AVRH, AVRL DVCC VI VO ICLAMP | ICLAMP | IOL1 IOLAV1 IOL2
IOLAV2 IOL1 IOL2 IOLAV1 IOLAV2 IOH1 IOHAV1 IOH2 IOHAV2 IOH1 IOH2 IOHAV1 IOHAV2
Rating Unit Min Max VSS - 0.3 VSS + 6.0 V VSS - 0.3 VSS + 6.0 V VCC = AVCC VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 -2.0 + 2.0 -- 20 -- 15 -- 4 -- 40 -- 30 -- 100 330 -- 50 250 -- -15 -- -4 -- -40 -- -30 -- -100 -- -330 -- -50 -- -250 -- 500 400 +85 +150 V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW mW C C
Remarks
*1 *1 *2 *2 *6 *6 *3 *4 *3 *4
Power supply voltage
AVCC AVRH/L, AVRH AVRL VCC DVCC
Input voltage Output voltage Max clamp current Total Max clamp current "L" level Max output current "L" level avg. output current "L" level Max output current "L" level avg. output current "L" level Max overall output current "L" level Max overall output current
"L" level avg. overall output current "L" level avg. overall output current
Normal output Normal output, average value High current output High current output, average value Total normal output Total high current output Total normal output, average value
Total high current output, average value
"H" level Max output current "H" level avg. output current "H" level Max output current "H" level avg. output current "H" level Max overall output current "H" level Max overall output current
"H" level avg. overall output current "H" level avg. overall output current
Normal output Normal output, average value High current output High current output, average value Total normal output Total high current output Total normal output, average value
*5 *5 *3 *4 *3 *4
Power consumption Operating temperature Storage temperature
PD
Total high current output, average value MB90F594A, MB90F591A, MB90F594G, MB90F591G
*5 *5
--
TA TSTG
MB90594, MB90591, MB90594G, MB90591G
-40 -55
*1 : AVCC, AVRH, AVRL and DVCC shall not exceed VCC. AVRH and AVRL shall not exceed AVCC. Also, AVRL shall not exceed AVRH. *2 : VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. (Continued)
36
MB90590/590G Series
*6 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 toP95 * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits
* Input/Output equivalent circuits
Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
Note : Average output current = operating current x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
37
MB90590/590G Series
2. Recommended Conditions
(VSS = AVSS = 0.0 V) Parameter Value
Symbol
Min 4.5
Typ 5.0
Max 5.5
Unit
Remarks
MB90V590A
V
Under normal operation MB90V590G Maintains RAM data in stop mode
MB90F594A MB90F594G MB90594 MB90594G
Power supply voltage
VCC AVCC
3.0 4.75 3.0
-- 5.0 -- 0.1 --
5.5 5.25 5.25 1.0 +85
V V V F C
Under normal operation MB90F591G MB90591G Maintains RAM data in MB90F591A stop mode MB90591 *
Smooth capacitor Operating temperature
CS TA
0.022 -40
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
* C Pin Connection Diagram
C CS
38
MB90590/590G Series
3. DC Characteristics
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Typ Max Input H voltage VIHS VIHM VILS Input L voltage VILM VILR Output H voltage VOH1 VOH2 VOL1 VOL2 IIL IIAL CMOS hysteresis input MD input CMOS hysteresis input MD input RST, HST Normal output -- -- -- -- -- VCC = 4.5 V, IOH1 = -4.0 mA 0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5 VCC - 0.5 -- -- -5 -1 -- -- -- -- -- -- -- -- -- -- -- -- -- ICCH VCC = 5.0 V10%, At Stop mode, TA = 25C -- -- -- -- -- -- -- -- -- -- -- -- -- -- 37 50 50 45 13 15 15 15 0.3 0.35 0.35 0.35 5 5 5 5 VCC +0.3 VCC +0.3 0.5VCC VSS + 0.3 0.2VCC -- -- 0.4 0.5 5 1 60 80 80 60 20 23 23 23 0.6 0.6 0.6 0.6 20 20 20 20 V V V V V V V V V A A mA mA mA mA mA mA mA mA mA mA mA mA A A A A
MB90594/594G MB90F594A/F594G MB90F591A/F591G MB90591/591G MB90594/594G MB90F594A/F594G MB90F591A/F591G MB90591/591G MB90594/594G MB90F594A/F594G MB90F591A/F591G MB90591/591G MB90594/594G MB90F594A/F594G MB90F591A/F591G MB90591/591G
High current VCC = 4.5 V, output IOH2 = -30.0 mA Normal output VCC = 4.5 V, IOL1 = 4.0 mA
Output L voltage Input leak current Analog input leak current
High current VCC = 4.5 V, output IOL2 = 30.0 mA -- AN0 to AN7 VCC = 5.5 V, VSS < VI < VCC VCC = 5.5 V, AVSS < VI < AVCC VCC = 5.0 V10%, Internal frequency : 16 MHz, At normal operation. VCC = 5.0 V10%, Internal frequency : 16 MHz, At Sleep mode. VCC VCC = 5.0 V10%, Internal frequency : 2 MHz, At Timer mode
ICC
ICCS Power supply current * ICTS
* : The power supply current testing conditions are when using the external clock.
(Continued)
39
MB90590/590G Series
(Continued)
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Parameter Symbol Pin name Min Typ Max
Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, P70 to P87 P70 to P87
Input capacity
CIN
--
--
5
15
pF
-- -- --
-- 25 25
15 50 50
30 100 100
pF k k
Pull-up resistance Pull-down resistance
RUP
RST
RDOWN MD2
40
MB90590/590G Series
4. AC Characteristics
(1) Clock Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin Unit Remarks Parameter Symbol name Min Typ Max Oscillation frequency Oscillation cycle time Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time Flash read cycle time fC tCYL PWH, PWL tCR, tCF fCP tCP tCYCFL X0, X1 X0 X0 -- -- -- 3 10 -- 1.5 62.5 -- -- -- -- -- -- -- 2 tCP 16 333 -- 5 16 666 -- MHz ns ns ns MHz ns ns When Flash is accessed by CPU Duty ratio is about 30 to 70%. When using external clock X0, X1 62.5
* Clock Timing
tCYL 0.8 VCC
X0 PWH tCF Example of Oscillation circuit PWL tCR
0.2 VCC
X0
X1
R
C1
C2
41
MB90590/590G Series
* Guaranteed operation range
Guaranteed operation range (MB90F591G, MB90591G, MB90F591A, MB90591) Guaranteed operation range (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G) 5.5 5.25 4.75 4.5
Power supply voltage VCC (V)
3.0
Guaranteed PLL operation range (MB90F591G, MB90591G, MB90F591A, MB90591) Guaranteed PLL operation range (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G)
1.5
8
16
Machine clock
fCP (MHz)
* Oscillation clock frequency and machine clock frequency x4 x3 x2 x1
16 12 Machine clock fCP (MHz) 9 8
x1/2 (PLL off)
4
3
4
8 Oscillation frequency fC (MHz)
16
42
MB90590/590G Series
(2) Reset and Hardware Standby Input (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Unit Remarks Parameter Min Max 16 tCP*1 Reset input time Hardware standby input time tRSTL tHSTL RST HST Oscillation time of oscillator*2 + 16 tCP*1 16 tCP*1 -- -- -- ns ms ns Under normal operation In stop mode Under normal operation
*1 : "tcp" represents one cycle time of the machine clock. No reset can fully initialize the Flash Memory if it is performing the automatic algorithm. *2 : Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. Under Normal Operation tRSTL, tHSTL RST HST
0.2 VCC
0.2 VCC
In Stop Mode
tRSTL RST 0.2VCC 0.2VCC
90% of amplitude
X0
Internal operation clock
16 tCP Oscillation time of
oscillator Internal reset
Oscillation setting time
Instruction execution
43
MB90590/590G Series
(3) Power On Reset (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Power on rise time Power off time tR tOFF VCC VCC -- 0.05 50 30 -- ms ms Due to repetitive operation
Notes : * VCC must be kept lower than 0.2 V before power-on. * The above values are used for creating a power-on reset. * Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power supply using the above values.
tR
VCC 0.2 V
2.7 V 0.2 V tOFF
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.
0.2 V
VCC 3V
RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
VSS
44
MB90590/590G Series
(4) UART0/1/2, Serial I/O (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SCK0 to SCK3 SCK0 to SCK3, SOT0 to SOT3 Internal clock operaSCK0 to SCK3, tion output pins are CL = 80 pF + 1 TTL. SIN0 to SIN3 SCK0 to SCK3, SIN0 to SIN3 SCK0 to SCK3 SCK0 to SCK3 SCK0 to SCK3, External clock operSOT0 to SOT3 ation output pins are SCK0 to SCK3, CL = 80 pF + 1 TTL. SIN0 to SIN3 SCK0 to SCK3, SIN0 to SIN3 8 tCP* -80 100 60 4 tCP 4 tCP -- 60 60 -- 80 -- -- -- -- 150 -- -- ns ns ns ns ns ns ns ns ns
* : tCP is the machine cycle (Unit : ns) Notes : * AC characteristic in CLK synchronized mode. * CL is load capacity value of pins when testing. * Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.5 VCC tSHIX 0.8 VCC 0.5 VCC 0.8 V
45
MB90590/590G Series
* External Shift Clock Mode tSLSH SCK 0.5 VCC 0.5 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.5 VCC tSHIX 0.8 VCC 0.5 VCC tSHSL 0.8 VCC 0.8 VCC
(5)Timer Input Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Input pulse width tTIWH tTIWL TIN0 IN0 to IN5 -- 4 tCP 1 -- -- ns s Under normal operation In stop mode
* Timer Input Timing
0.8 VCC tTIWH
0.8 VCC 0.5 VCC tTIWL 0.5 VCC
46
MB90590/590G Series
(6)Trigger Input Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Input pulse width tTRGH tTRGL INT0 to INT7, ADTG -- 5 tCP -- ns
* Trigger Input Timing
0.8 VCC tTRGH
0.8 VCC 0.5 VCC tTRGL 0.5 VCC
(7) Slew Rate High Current Outputs (MB90F591G, MB90591G, MB90F591A, MB90591, MB90594G and MB90F594G only) (MB90F594G, MB90594G : VCC = 5.0 V10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V5 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Output Rise/Fall time tR2 tF2 Port P70 to P77, Port P80 to P87 -- 15 40 ns
* Slew Rate Output Timing
VH VL VH VL
VH = VOL2 + 0.1 x (VOH2 - VOL2) VL = VOL2 + 0.9 x (VOH2 - VOL2)
tR2
tF2
47
MB90590/590G Series
5. A/D Converter
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = AVCC = 5.0 V10 %, VSS = AVSS = 0.0 V, 3.0 V AVR+ - AVR-, TA = -40 C to +85 C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = AVCC = 5.0 V5 %, VSS = AVSS = 0.0 V, 3.0 V AVR+ - AVR-, TA = -40 C to +85 C) Value Parameter Symbol Pin name Unit Remarks Min Typ Max Resolution Conversion error Nonlinearity error Differential linearity error Zero transition voltage Full scale transition voltage -- -- -- -- VOT VFST -- -- -- -- AN0 to AN7 AN0 to AN7 -- -- -- -- AVRL - 3.5 LSB AVRH - 6.5 LSB 352tCP -- -- -- -- AVRL + 0.5 LSB AVRH - 1.5 LSB -- 10 5.0 2.5 1.9 AVRL + 4.5 LSB AVRH + 1.5 LSB -- bit LSB LSB LSB mV mV Internal frequency : 16 MHz Internal frequency : 16 MHz
Compare time
--
--
ns
Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current
-- IAIN VAIN -- -- IA IAH
-- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC
64tCP -1 AVRL AVRL + 2.7 0 -- --
-- -- -- -- -- 5 --
-- +1 AVRH AVCC AVRH - 2.7 -- 5
ns A V V V mA A
* MB90594 MB90V590A MB90V590G MB90F594A MB90F594G MB90F591A MB90F591G MB90594G MB90591 MB90591G *
-- Reference voltage current IR AVRH
400
600
A
-- IRH Offset between input channels -- AVRH AN0 to AN7 -- --
140 -- --
600 5 4
A A LSB
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
48
MB90590/590G Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error 3FF 3FE 3FD Actual conversion value 0.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
Digital output
004 003 002 001
VNT (measured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB
1 LSB = (Theoretical value)
AVRH - AVRL 1024
[V]
Total error for digital output N =
[LSB]
VOT (Theoretical value) = AVRL + 0.5 LSB[V] VFST (Theoretical value) = AVRH - 1.5 LSB[V]
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
49
MB90590/590G Series
(Continued)
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x (N - 1)+ VOT} VFST (measured value) N+1 Actual conversion value Differential linearity error Theoretical characteristics
Digital output
Digital output
N
004 003 002 001
VNT (measured value) Actual conversion characteristics
N-1
V(N + 1)T (measured value) VNT (measured value)
Theoretical characteristics VOT (measured value) AVRL Analog input AVRH
N-2
Actual conversion value
AVRL
Analog input
AVRH
VNT - {1 LSB x (N - 1) + VOT} Linearity error of [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = VFST - VOT 1022 [V] V(N + 1)T - VNT 1 LSB - 1 LSB [LSB]
VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH"
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions, : * Output impedance values of the external circuit of 15 k or lower are recommended. * When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Equipment of analog input circuit model
Analog input Comparator 3.2 k Max 30 pF Max
Note : Listed values must be considered as standards.
* Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 50
MB90590/590G Series
8. Flash Memory
* Erase and Programming Performance Value Parameter Condition Min Typ Max Sector erase time Chip erase time Word (16-bit) programming time Erase/Program cycle -- TA = + 25 C VCC = 5.0 V -- -- -- -- 10,000 1 7 12 16 -- 15 -- -- 3,600 -- Unit s s s ns cycle Remarks Excludes 00H programming prior erasure MB90F594A/F594G Excludes 00H programming MB90F591A/F591G prior erasure Excludes system-level overhead
51
MB90590/590G Series
s EXAMPLE CHARACTERISTICS
* "H" Level Output Voltage
VOH1 - IOH1
5 4.5 4 3.5 (Vcc = 4.5 V, TA = +25C) 5 4.5 4 3.5
VOH2 - IOH2
(Vcc = 4.5 V, TA = +25C)
VOH1 [V]
VOH2 [V]
0.0 -2.0 -4.0 -6.0 -8.0 -10.0
3 2.5 2 1.5 1 0.5 0
3 2.5 2 1.5 1 0.5 0 0 -10 -20 -30 -40
IOH1 [mA]
IOH2 [mA]
* "L" Level Output Voltage
VOL1 - IOL1 (Vcc = 4.5 V, TA = +25C)
0.8 0.7 0.6
VOL2 - IOL2 (Vcc = 4.5 V, TA = +25C)
0.8 0.7 0.6
VOL1 [V]
0.5 0.4 0.3 0.2 0.1 0 0.0
VOL2 [V]
0.5 0.4 0.3 0.2 0.1 0
2.0
4.0
6.0
8.0
10.0
0.0
10.0
20.0
30.0
40.0
IOL1 [mA]
IOL2 [mA]
* "H" Level Input Voltage/"L Level Input Voltage (Hysteresis Input)
VIN - VCC
5 (TA = +25C)
4
VIH VIL
VIN [V]
3
2
1
0
3
4
5
6
Vcc [V]
(Continued)
52
MB90590/590G Series
(Continued)
* Power Supply Voltage
ICC - VCC
(TA = +25C) 60 fcp = 16 MHz 50
ICCS - VCC
(TA = +25C) 25 fcp = 16 MHz 20
ICC [mA]
40 30 20 fcp = 4 MHz 10 0
ICCS [mA]
15 fcp = 8 MHz 10 fcp = 4 MHz 5 fcp = 2 MHz
fcp = 8 MHz
fcp = 2 MHz 2.0 3.0 4.0 5.0 6.0 7.0
0 2.0 3.0 4.0 5.0 6.0 7.0
VCC [V]
VCC [V]
ICTS - VCC
800 700 600 500
ICCH - VCC
(TA = +25C)
fcp = 4 MHz
20 18 16
(TA = +25C)
ICCT [mA]
14 12 10 8 6 4
ICTS [mA]
fcp = 2 MHz 400 300 200 100 0 2.0 3.0 4.0 5.0 6.0 7.0
2 0 2.0 3.0 4.0 5.0 6.0 7.0
VCC [V]
VCC [V]
53
MB90590/590G Series
s ORDERING INFORMATION
Part number MB90594PF MB90591PF MB90594GPF MB90F594GPF MB90F594APF MB90F591APF MB90F591GPF MB90591GPF MB90V590ACR MB90V590GCR Package Remarks
100-pin Plastic QFP (FPT-100P-M06)
256-pin Ceramic PGA (PGA-256C-A01)
For evaluation
54
MB90590/590G Series
s PACKAGE DIMENSION
100-pin plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 51
81
50
0.10(.004) 17.900.40 (.705.016) 14.000.20 (.551.008) INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off)
0.65(.026)
0.320.05 (.013.002)
0.13(.005)
M
"A"
C
2001 FUJITSU LIMITED F100008S-c-4-4
Dimensions in mm (inches)
55
MB90590/590G Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0204 (c) FUJITSU LIMITED Printed in Japan

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